This invention relates to electronic assembly technology and more specifically to interconnections on semiconductor wafers.
A sophisticated and widely used interconnection technology has been developed for connecting one electrical site on a semiconductor wafer to another. Typically these interconnections involve connecting the active elements of a semiconductor device, e.g. source, drain, gate to each other, or to another device, or to a runner that interconnects to another level. In early device technology, and in some simple large area devices in current production, these interconnections are made on a single level on the surface of the semiconductor wafer. As device dimensions have been reduced, and the complexity of interconnections increased, multiple level interconnections were developed. These are stacked on the semiconductor wafer surface over the active devices. Three or even four levels of interconnection are not uncommon.
Recently, new technologies have arisen where one or more interconnect levels are formed directly on the semiconductor surface, and active device located above the interconnect levels. However, in both of these cases all of the device structure, including the interconnections, are located on the same side of the wafer.
New photonic devices are in development that use micromechanical elements. In principal micromechanical elements can be built on a variety of platforms, not necessarily semiconductor platforms. However, highly and often elegantly engineered silicon processing can be used to make new device structures that combine mainly the mechanical and optical properties of silicon. Consequently, so-called silicon optical bench technology has evolved in which the platform for the micromechanical devices or subassemblies is a silicon wafer, or a large silicon chip.
Among the most promising of the photonic micromechanical devices are optical switches. These devices typically comprise mirrors, and the mirrors operate as moving parts. The movement of the mirrors in these devices may be effected by magnetic or electric fields, both activated using electrical circuitry. To date, the electrical circuits have been built around the micromechanical elements to interconnect them together. As the micromechanical elements shrink in size, and the electrical circuits that drive them become more complex, the option of building interconnect layers on top of the active structures, as in state of the art IC technology, is limited by both the need for movement of the micromechanical elements and the need for accessing these elements, e.g., mirrors, with optical beams. The solution to interconnect congestion in large micro-mirror arrays to date has been to increase the platform area.
We have developed an interconnect technology for micromechanical devices in which the micromechanical elements are located on the top side of the silicon wafer platform but most of the interconnection for the electrical circuits that drive the micromechanical elements is located on the backside, i.e. bottom side, of the silicon wafer. This interconnect strategy leads to several important advantages. It provides more area for interconnections. It allows for multilevel interconnect layers. It provides space, with concomitant short interconnections, for attachment of active drive IC devices. It removes a source of stray electromagnetic fields from the top surface, where the electrostatic drive elements for mirror tilt are susceptible to unwanted interactions, to the bottom surface remote from the mirror tilt apparatus. According to the invention, the interconnections are made using through holes that extend from the front side of the silicon wafer to the backside through the thickness of the silicon wafer. The walls of the through holes are first coated with insulator, and the remaining hole is plugged with a conductive material, preferably polysilicon. The choice of polysilicon is advantageous for thermo-mechanical integrity of the wafer.